library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library altera;
use altera.altera_primitives_components.all;


entity shift_table is
	port(clock,ctrl_writeEN,ctrl_shiftEN,ctrl_reset :in std_logic;
		ctrl_writeReg,ctrl_readReg,ctrl_shiftReg :in std_logic_vector(0 to 31);
		data_searchaddr : in std_logic_vector(0 to 47);
		data_inaddr : in std_logic_vector(0 to 47);
		data_inport : in std_logic_vector(0 to 1);
		data_outport: out std_logic_vector(0 to 1);
		data_location: out std_logic_vector(0 to 31);
		data_found: out std_logic);
end shift_table;

architecture struct of shift_table is

	component shiftdecode is 
		port(enable: in std_logic;
		e: in std_logic_vector(0 to 31);
		d: out std_logic_vector(0 to 31));
	end component;
	
	component reg50bit is
	port(clock,write_en,read_en,shift,reset : in std_logic;
		data_search : in std_logic_vector(0 to 47);
		data_write, data_inshift : in std_logic_vector(0 to 49);
		data_outshift : out std_logic_vector(0 to 49);
		data_read : out std_logic_vector(48 to 49);
		data_found: out std_logic);
	end component;
	
	type arr is array(0 to 31) of std_logic_vector(0 to 49);
	signal ctrl_read,ctrl_write,ctrl_shift:std_logic_vector(0 to 31);
	signal found: std_logic_vector(0 to 31);
	signal shiftarray: arr;
begin
	shift_decode: shiftdecode port map(enable=>'1',e=>ctrl_shiftReg,d=>ctrl_shift);
	registers:
		for i in 0 to 30 generate
		reg: reg50bit port map(
					  clock=>clock,
					  write_en=>(ctrl_writeEN and ctrl_writeReg(i)),
					  read_en=>ctrl_readReg(i),
					  shift=>(ctrl_shiftEN and ctrl_shift(i)),
					  reset=>ctrl_reset,
					  data_search => data_searchaddr,
					  data_write(0 to 47)=>data_inaddr,
					  data_write(48 to 49)=>data_inport,
					  data_inshift=>shiftarray(i+1),
					  data_read=>data_outport,
					  data_outshift=>shiftarray(i),
					  data_found => found(i));
		end generate;
	reg31: 	reg50bit port map(
				  clock=>clock,
				  write_en=>(ctrl_writeEN and ctrl_writeReg(31)),
				  read_en=>ctrl_readReg(31),
				  shift=>'0',
				  reset=>ctrl_reset,
				  data_search => data_searchaddr,
				  data_write(0 to 47)=>data_inaddr,
				  data_write(48 to 49) => data_inport,
				  data_inshift=>shiftarray(31),
				  data_read=>data_outport,
				  data_outshift=>shiftarray(31),
				  data_found => found(31));
	
	data_found <= found(0) or found(1) or found(2) or found(3) or found(4) or found(5) or 
				  found(6) or found(7) or found(8) or found(9) or found(10) or found(11) or 
				  found(12) or found(13) or found(14) or found(15) or found(16) or found(17) or 
				  found(18) or found(19) or found(20) or found(21) or found(22) or found(23) or 
				  found(24) or found(25) or found(26) or found(27) or found(28) or found(29) or 
				  found(30) or found(31);
	data_location <= found;
end struct;